Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	100546293	1			T1	214343		T2	17265		T3	6
all_pins[1]	100546293	1			T1	214343		T2	17265		T3	6
all_pins[2]	100546293	1			T1	214343		T2	17265		T3	6

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	300803836	1			T1	642487		T2	51590		T3	18
values[0x1]	835043	1			T1	542		T2	205		T7	5685
transitions[0x0=>0x1]	833011	1			T1	542		T2	205		T7	5646
transitions[0x1=>0x0]	833033	1			T1	542		T2	205		T7	5646

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	100035394	1			T1	213801		T2	17105		T3	6
all_pins[0]	values[0x1]	510899	1			T1	542		T2	160		T7	624
all_pins[0]	transitions[0x0=>0x1]	510889	1			T1	542		T2	160		T7	624
all_pins[0]	transitions[0x1=>0x0]	5736	1			T2	45		T7	130		T20	85
all_pins[1]	values[0x0]	100540547	1			T1	214343		T2	17220		T3	6
all_pins[1]	values[0x1]	5746	1			T2	45		T7	130		T20	85
all_pins[1]	transitions[0x0=>0x1]	5636	1			T2	45		T7	123		T20	85
all_pins[1]	transitions[0x1=>0x0]	318288	1			T7	4924		T21	743		T40	1308
all_pins[2]	values[0x0]	100227895	1			T1	214343		T2	17265		T3	6
all_pins[2]	values[0x1]	318398	1			T7	4931		T21	743		T40	1308
all_pins[2]	transitions[0x0=>0x1]	316486	1			T7	4899		T21	743		T40	1308
all_pins[2]	transitions[0x1=>0x0]	509009	1			T1	542		T2	160		T7	592