Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
11023093 |
1 |
|
|
T1 |
2992 |
|
T2 |
17637 |
|
T7 |
60083 |
auto[1] |
11023079 |
1 |
|
|
T1 |
2992 |
|
T2 |
17637 |
|
T7 |
60083 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
21804694 |
1 |
|
|
T1 |
5984 |
|
T2 |
35120 |
|
T7 |
119648 |
triple_byte_access |
80152 |
1 |
|
|
T2 |
58 |
|
T7 |
174 |
|
T35 |
620 |
halfword_access |
81264 |
1 |
|
|
T2 |
50 |
|
T7 |
190 |
|
T35 |
632 |
byte_access |
80062 |
1 |
|
|
T2 |
46 |
|
T7 |
154 |
|
T35 |
620 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10902354 |
1 |
|
|
T1 |
2992 |
|
T2 |
17560 |
|
T7 |
59824 |
auto[0] |
triple_byte_access |
40076 |
1 |
|
|
T2 |
29 |
|
T7 |
87 |
|
T35 |
310 |
auto[0] |
halfword_access |
40632 |
1 |
|
|
T2 |
25 |
|
T7 |
95 |
|
T35 |
316 |
auto[0] |
byte_access |
40031 |
1 |
|
|
T2 |
23 |
|
T7 |
77 |
|
T35 |
310 |
auto[1] |
word_access |
10902340 |
1 |
|
|
T1 |
2992 |
|
T2 |
17560 |
|
T7 |
59824 |
auto[1] |
triple_byte_access |
40076 |
1 |
|
|
T2 |
29 |
|
T7 |
87 |
|
T35 |
310 |
auto[1] |
halfword_access |
40632 |
1 |
|
|
T2 |
25 |
|
T7 |
95 |
|
T35 |
316 |
auto[1] |
byte_access |
40031 |
1 |
|
|
T2 |
23 |
|
T7 |
77 |
|
T35 |
310 |