Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	101033815	1			T2	1010		T3	156235		T17	457787
all_values[1]	101033815	1			T2	1010		T3	156235		T17	457787
all_values[2]	101033815	1			T2	1010		T3	156235		T17	457787

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

588501

1

T2

60

T3

3398

T17

3

auto[1]

302512944

1

T2

2970

T3

465307

T17

137335

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

301576068

1

T2

2574

T3

468258

T17

136325

auto[1]

1525377

1

T2

456

T3

447

T17

10110

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	239393	1			T17	1		T35	1		T7	239
all_values[0]	auto[0]	auto[1]	2053	1			T17	2		T35	2		T7	10
all_values[0]	auto[1]	auto[0]	100285963	1			T2	858		T3	156086		T17	454416
all_values[0]	auto[1]	auto[1]	506406	1			T2	152		T3	149		T17	3368
all_values[1]	auto[0]	auto[0]	156382	1			T2	12		T3	5		T34	5
all_values[1]	auto[0]	auto[1]	1599	1			T2	1		T3	1		T34	2
all_values[1]	auto[1]	auto[0]	100368974	1			T2	846		T3	156081		T17	454417
all_values[1]	auto[1]	auto[1]	506860	1			T2	151		T3	148		T17	3370
all_values[2]	auto[0]	auto[0]	187655	1			T2	41		T3	3387		T35	4
all_values[2]	auto[0]	auto[1]	1419	1			T2	6		T3	5		T35	3
all_values[2]	auto[1]	auto[0]	100337701	1			T2	817		T3	152699		T17	454417
all_values[2]	auto[1]	auto[1]	507040	1			T2	146		T3	144		T17	3370