Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
291580 |
1 |
|
|
T2 |
194 |
|
T3 |
202 |
|
T17 |
2 |
auto[1] |
400638 |
1 |
|
|
T17 |
4528 |
|
T34 |
4672 |
|
T7 |
70 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
172984 |
1 |
|
|
T2 |
51 |
|
T3 |
62 |
|
T17 |
1160 |
lower_val |
170569 |
1 |
|
|
T2 |
48 |
|
T3 |
50 |
|
T17 |
1160 |
zero_val |
1762 |
1 |
|
|
T2 |
1 |
|
T3 |
3 |
|
T17 |
3 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
246192 |
1 |
|
|
T2 |
108 |
|
T3 |
96 |
|
T17 |
1144 |
lower_val |
245012 |
1 |
|
|
T2 |
86 |
|
T3 |
106 |
|
T17 |
1172 |
zero_val |
201014 |
1 |
|
|
T17 |
2214 |
|
T34 |
2380 |
|
T7 |
28 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
36377 |
1 |
|
|
T2 |
29 |
|
T3 |
28 |
|
T35 |
57 |
higher_val |
higher_val |
auto[1] |
25228 |
1 |
|
|
T17 |
291 |
|
T34 |
278 |
|
T7 |
5 |
higher_val |
lower_val |
auto[0] |
36126 |
1 |
|
|
T2 |
22 |
|
T3 |
34 |
|
T35 |
45 |
higher_val |
lower_val |
auto[1] |
24953 |
1 |
|
|
T17 |
311 |
|
T34 |
297 |
|
T7 |
3 |
higher_val |
zero_val |
auto[0] |
82 |
1 |
|
|
T9 |
2 |
|
T43 |
1 |
|
T59 |
1 |
higher_val |
zero_val |
auto[1] |
50218 |
1 |
|
|
T17 |
558 |
|
T34 |
575 |
|
T7 |
4 |
lower_val |
higher_val |
auto[0] |
36017 |
1 |
|
|
T2 |
25 |
|
T3 |
25 |
|
T35 |
59 |
lower_val |
higher_val |
auto[1] |
24767 |
1 |
|
|
T17 |
299 |
|
T34 |
293 |
|
T7 |
4 |
lower_val |
lower_val |
auto[0] |
35600 |
1 |
|
|
T2 |
23 |
|
T3 |
25 |
|
T35 |
57 |
lower_val |
lower_val |
auto[1] |
24437 |
1 |
|
|
T17 |
277 |
|
T34 |
334 |
|
T7 |
4 |
lower_val |
zero_val |
auto[0] |
71 |
1 |
|
|
T9 |
2 |
|
T44 |
1 |
|
T179 |
1 |
lower_val |
zero_val |
auto[1] |
49677 |
1 |
|
|
T17 |
584 |
|
T34 |
561 |
|
T7 |
4 |
zero_val |
higher_val |
auto[0] |
494 |
1 |
|
|
T2 |
1 |
|
T3 |
2 |
|
T35 |
1 |
zero_val |
higher_val |
auto[1] |
170 |
1 |
|
|
T17 |
1 |
|
T34 |
2 |
|
T7 |
2 |
zero_val |
lower_val |
auto[0] |
502 |
1 |
|
|
T3 |
1 |
|
T17 |
1 |
|
T35 |
2 |
zero_val |
lower_val |
auto[1] |
131 |
1 |
|
|
T17 |
1 |
|
T34 |
1 |
|
T9 |
1 |
zero_val |
zero_val |
auto[0] |
242 |
1 |
|
|
T34 |
1 |
|
T9 |
3 |
|
T43 |
1 |
zero_val |
zero_val |
auto[1] |
223 |
1 |
|
|
T34 |
1 |
|
T39 |
1 |
|
T45 |
1 |