Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	101033815	1			T2	1010		T3	156235		T17	457787
all_pins[1]	101033815	1			T2	1010		T3	156235		T17	457787
all_pins[2]	101033815	1			T2	1010		T3	156235		T17	457787

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	302319624	1			T2	2878		T3	468556		T17	136999
values[0x1]	781821	1			T2	152		T3	149		T17	3368
transitions[0x0=>0x1]	780007	1			T2	152		T3	149		T17	3368
transitions[0x1=>0x0]	780022	1			T2	152		T3	149		T17	3368

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	100527409	1			T2	858		T3	156086		T17	454419
all_pins[0]	values[0x1]	506406	1			T2	152		T3	149		T17	3368
all_pins[0]	transitions[0x0=>0x1]	506391	1			T2	152		T3	149		T17	3368
all_pins[0]	transitions[0x1=>0x0]	5468	1			T9	104		T40	6		T18	20
all_pins[1]	values[0x0]	101028332	1			T2	1010		T3	156235		T17	457787
all_pins[1]	values[0x1]	5483	1			T9	104		T40	6		T18	20
all_pins[1]	transitions[0x0=>0x1]	5329	1			T9	92		T40	6		T18	20
all_pins[1]	transitions[0x1=>0x0]	269778	1			T7	737		T9	5089		T16	3255
all_pins[2]	values[0x0]	100763883	1			T2	1010		T3	156235		T17	457787
all_pins[2]	values[0x1]	269932	1			T7	737		T9	5101		T16	3255
all_pins[2]	transitions[0x0=>0x1]	268287	1			T7	734		T9	5067		T16	3233
all_pins[2]	transitions[0x1=>0x0]	504776	1			T2	152		T3	149		T17	3368