Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10796619 |
1 |
|
|
T2 |
3737 |
|
T3 |
16329 |
|
T17 |
47900 |
auto[1] |
10796619 |
1 |
|
|
T2 |
3737 |
|
T3 |
16329 |
|
T17 |
47900 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
21355398 |
1 |
|
|
T2 |
7350 |
|
T3 |
32508 |
|
T17 |
93928 |
triple_byte_access |
79008 |
1 |
|
|
T2 |
46 |
|
T3 |
56 |
|
T17 |
620 |
halfword_access |
79670 |
1 |
|
|
T2 |
42 |
|
T3 |
50 |
|
T17 |
632 |
byte_access |
79162 |
1 |
|
|
T2 |
36 |
|
T3 |
44 |
|
T17 |
620 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10677699 |
1 |
|
|
T2 |
3675 |
|
T3 |
16254 |
|
T17 |
46964 |
auto[0] |
triple_byte_access |
39504 |
1 |
|
|
T2 |
23 |
|
T3 |
28 |
|
T17 |
310 |
auto[0] |
halfword_access |
39835 |
1 |
|
|
T2 |
21 |
|
T3 |
25 |
|
T17 |
316 |
auto[0] |
byte_access |
39581 |
1 |
|
|
T2 |
18 |
|
T3 |
22 |
|
T17 |
310 |
auto[1] |
word_access |
10677699 |
1 |
|
|
T2 |
3675 |
|
T3 |
16254 |
|
T17 |
46964 |
auto[1] |
triple_byte_access |
39504 |
1 |
|
|
T2 |
23 |
|
T3 |
28 |
|
T17 |
310 |
auto[1] |
halfword_access |
39835 |
1 |
|
|
T2 |
21 |
|
T3 |
25 |
|
T17 |
316 |
auto[1] |
byte_access |
39581 |
1 |
|
|
T2 |
18 |
|
T3 |
22 |
|
T17 |
310 |