Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	100128579	1			T1	36		T2	224826		T3	49475
all_values[1]	100128579	1			T1	36		T2	224826		T3	49475
all_values[2]	100128579	1			T1	36		T2	224826		T3	49475

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

415305

1

T1

3

T3

3986

T15

95

auto[1]

299970432

1

T1

105

T2

674478

T3

144439

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

298858020

1

T1

108

T2

672672

T3

146529

auto[1]

1527717

1

T2

1806

T3

1896

T15

42

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	114997	1			T3	358		T15	4		T37	3
all_values[0]	auto[0]	auto[1]	1860	1			T3	10		T15	2		T37	2
all_values[0]	auto[1]	auto[0]	99504343	1			T1	36		T2	224224		T3	48485
all_values[0]	auto[1]	auto[1]	507379	1			T2	602		T3	622		T15	12
all_values[1]	auto[0]	auto[0]	123100	1			T1	3		T3	2291		T37	3
all_values[1]	auto[0]	auto[1]	1430	1			T3	26		T37	2		T20	6
all_values[1]	auto[1]	auto[0]	99496240	1			T1	33		T2	224224		T3	46552
all_values[1]	auto[1]	auto[1]	507809	1			T2	602		T3	606		T15	14
all_values[2]	auto[0]	auto[0]	172406	1			T3	1281		T15	83		T38	2
all_values[2]	auto[0]	auto[1]	1512	1			T3	20		T15	6		T38	1
all_values[2]	auto[1]	auto[0]	99446934	1			T1	36		T2	224224		T3	47562
all_values[2]	auto[1]	auto[1]	507727	1			T2	602		T3	612		T15	8