Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
374656 |
1 |
|
|
T1 |
2 |
|
T2 |
2 |
|
T3 |
488 |
auto[1] |
317470 |
1 |
|
|
T1 |
68 |
|
T2 |
778 |
|
T3 |
430 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
172977 |
1 |
|
|
T1 |
15 |
|
T2 |
236 |
|
T3 |
243 |
lower_val |
171681 |
1 |
|
|
T1 |
20 |
|
T2 |
179 |
|
T3 |
235 |
zero_val |
1791 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
12 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
267390 |
1 |
|
|
T1 |
24 |
|
T2 |
222 |
|
T3 |
348 |
lower_val |
265810 |
1 |
|
|
T1 |
10 |
|
T2 |
184 |
|
T3 |
346 |
zero_val |
158926 |
1 |
|
|
T1 |
36 |
|
T2 |
374 |
|
T3 |
224 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
46977 |
1 |
|
|
T2 |
1 |
|
T3 |
64 |
|
T37 |
10 |
higher_val |
higher_val |
auto[1] |
19909 |
1 |
|
|
T1 |
9 |
|
T2 |
61 |
|
T3 |
28 |
higher_val |
lower_val |
auto[0] |
46801 |
1 |
|
|
T3 |
57 |
|
T37 |
10 |
|
T38 |
567 |
higher_val |
lower_val |
auto[1] |
19801 |
1 |
|
|
T1 |
2 |
|
T2 |
63 |
|
T3 |
36 |
higher_val |
zero_val |
auto[0] |
80 |
1 |
|
|
T16 |
1 |
|
T193 |
1 |
|
T13 |
1 |
higher_val |
zero_val |
auto[1] |
39409 |
1 |
|
|
T1 |
4 |
|
T2 |
111 |
|
T3 |
58 |
lower_val |
higher_val |
auto[0] |
46602 |
1 |
|
|
T3 |
58 |
|
T37 |
12 |
|
T38 |
569 |
lower_val |
higher_val |
auto[1] |
19967 |
1 |
|
|
T1 |
8 |
|
T2 |
44 |
|
T3 |
20 |
lower_val |
lower_val |
auto[0] |
46274 |
1 |
|
|
T1 |
1 |
|
T3 |
69 |
|
T15 |
1 |
lower_val |
lower_val |
auto[1] |
19624 |
1 |
|
|
T1 |
1 |
|
T2 |
38 |
|
T3 |
26 |
lower_val |
zero_val |
auto[0] |
82 |
1 |
|
|
T21 |
1 |
|
T41 |
1 |
|
T194 |
1 |
lower_val |
zero_val |
auto[1] |
39132 |
1 |
|
|
T1 |
10 |
|
T2 |
97 |
|
T3 |
62 |
zero_val |
higher_val |
auto[0] |
562 |
1 |
|
|
T2 |
1 |
|
T3 |
3 |
|
T38 |
1 |
zero_val |
higher_val |
auto[1] |
125 |
1 |
|
|
T3 |
2 |
|
T86 |
1 |
|
T193 |
1 |
zero_val |
lower_val |
auto[0] |
576 |
1 |
|
|
T1 |
1 |
|
T3 |
2 |
|
T15 |
1 |
zero_val |
lower_val |
auto[1] |
114 |
1 |
|
|
T3 |
4 |
|
T86 |
1 |
|
T193 |
1 |
zero_val |
zero_val |
auto[0] |
256 |
1 |
|
|
T3 |
1 |
|
T36 |
1 |
|
T20 |
1 |
zero_val |
zero_val |
auto[1] |
158 |
1 |
|
|
T86 |
2 |
|
T50 |
3 |
|
T195 |
2 |