Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msg_len_cg

Group : kmac_env_pkg::kmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
msg_len	15	0	15	100.00	100	1	1	0

Summary for Variable msg_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	10346	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_7501_10000	8920	1			T2	17		T3	18		T36	31
len_5001_7500	14081	1			T2	17		T3	17		T36	92
len_2501_5000	9165	1			T2	17		T3	4		T36	22
len_1025_2500	5364	1			T2	10		T3	1		T36	8
len_769_1024	6174	1			T2	2		T3	67		T36	2
len_513_768	6680	1			T2	2		T3	89		T37	1
len_257_512	21149	1			T2	2		T3	85		T36	1
len_0_256	257616	1			T2	290		T3	134		T15	9
len_keccak_block_sizes[72]	724	1			T2	2		T3	1		T38	3
len_keccak_block_sizes[104]	612	1			T2	2		T38	3		T39	2
len_keccak_block_sizes[136]	527	1			T2	2		T38	3		T39	2
len_keccak_block_sizes[144]	427	1			T2	2		T3	1		T38	3
len_keccak_block_sizes[168]	327	1			T38	3		T86	3		T43	1
len_1	749	1			T2	2		T3	1		T38	3
len_0	1246	1			T2	2		T3	1		T36	7