Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	100128579	1			T1	36		T2	224826		T3	49475
all_pins[1]	100128579	1			T1	36		T2	224826		T3	49475
all_pins[2]	100128579	1			T1	36		T2	224826		T3	49475

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	299603575	1			T1	108		T2	673876		T3	136726
values[0x1]	782162	1			T2	602		T3	11699		T15	12
transitions[0x0=>0x1]	780293	1			T2	602		T3	11626		T15	12
transitions[0x1=>0x0]	780323	1			T2	602		T3	11626		T15	12

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	99621200	1			T1	36		T2	224224		T3	48853
all_pins[0]	values[0x1]	507379	1			T2	602		T3	622		T15	12
all_pins[0]	transitions[0x0=>0x1]	507362	1			T2	602		T3	622		T15	12
all_pins[0]	transitions[0x1=>0x0]	5659	1			T6	93		T18	57		T59	50
all_pins[1]	values[0x0]	100122903	1			T1	36		T2	224826		T3	49475
all_pins[1]	values[0x1]	5676	1			T6	93		T18	57		T59	50
all_pins[1]	transitions[0x0=>0x1]	5465	1			T6	93		T18	57		T59	50
all_pins[1]	transitions[0x1=>0x0]	268896	1			T3	11077		T6	1531		T21	127
all_pins[2]	values[0x0]	99859472	1			T1	36		T2	224826		T3	38398
all_pins[2]	values[0x1]	269107	1			T3	11077		T6	1531		T21	127
all_pins[2]	transitions[0x0=>0x1]	267466	1			T3	11004		T6	1531		T21	127
all_pins[2]	transitions[0x1=>0x0]	505768	1			T2	602		T3	549		T15	12