Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10656031 |
1 |
|
|
T1 |
1016 |
|
T2 |
2730 |
|
T3 |
62987 |
auto[1] |
10656031 |
1 |
|
|
T1 |
1016 |
|
T2 |
2730 |
|
T3 |
62987 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
21074018 |
1 |
|
|
T1 |
2032 |
|
T2 |
5460 |
|
T3 |
125382 |
triple_byte_access |
79338 |
1 |
|
|
T3 |
184 |
|
T36 |
92 |
|
T37 |
14 |
halfword_access |
79688 |
1 |
|
|
T3 |
194 |
|
T36 |
100 |
|
T37 |
24 |
byte_access |
79018 |
1 |
|
|
T3 |
214 |
|
T36 |
92 |
|
T37 |
24 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10537009 |
1 |
|
|
T1 |
1016 |
|
T2 |
2730 |
|
T3 |
62691 |
auto[0] |
triple_byte_access |
39669 |
1 |
|
|
T3 |
92 |
|
T36 |
46 |
|
T37 |
7 |
auto[0] |
halfword_access |
39844 |
1 |
|
|
T3 |
97 |
|
T36 |
50 |
|
T37 |
12 |
auto[0] |
byte_access |
39509 |
1 |
|
|
T3 |
107 |
|
T36 |
46 |
|
T37 |
12 |
auto[1] |
word_access |
10537009 |
1 |
|
|
T1 |
1016 |
|
T2 |
2730 |
|
T3 |
62691 |
auto[1] |
triple_byte_access |
39669 |
1 |
|
|
T3 |
92 |
|
T36 |
46 |
|
T37 |
7 |
auto[1] |
halfword_access |
39844 |
1 |
|
|
T3 |
97 |
|
T36 |
50 |
|
T37 |
12 |
auto[1] |
byte_access |
39509 |
1 |
|
|
T3 |
107 |
|
T36 |
46 |
|
T37 |
12 |