Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
92.59 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 2 16 88.89


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 2 16 88.89 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 296 1 T131 7 T132 7 T133 7
all_values[1] 296 1 T131 7 T132 7 T133 7
all_values[2] 296 1 T131 7 T132 7 T133 7


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 468 1 T131 9 T132 8 T133 16
auto[1] 420 1 T131 12 T132 13 T133 5


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 385 1 T131 5 T132 9 T133 10
auto[1] 503 1 T131 16 T132 12 T133 11


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 497 1 T131 12 T132 12 T133 12
auto[1] 391 1 T131 9 T132 9 T133 9


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 2 16 88.89 2
Automatically Generated Cross Bins 18 2 16 88.89 2
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Element holes
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTNUMBERSTATUS
[all_values[1]] [auto[0]] * [auto[1]] -- -- 2


Covered bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 67 1 T131 1 T132 1 T133 3
all_values[0] auto[0] auto[0] auto[1] 29 1 T131 2 T173 1 T174 1
all_values[0] auto[0] auto[1] auto[0] 43 1 T132 1 T173 1 T175 1
all_values[0] auto[0] auto[1] auto[1] 27 1 T131 1 T132 2 T176 1
all_values[0] auto[1] auto[0] auto[1] 79 1 T131 1 T132 2 T133 2
all_values[0] auto[1] auto[1] auto[1] 51 1 T131 2 T132 1 T133 2
all_values[1] auto[0] auto[0] auto[0] 82 1 T131 2 T132 3 T133 3
all_values[1] auto[0] auto[1] auto[0] 79 1 T131 2 T132 1 T133 2
all_values[1] auto[1] auto[0] auto[1] 59 1 T131 1 T132 1 T133 2
all_values[1] auto[1] auto[1] auto[1] 76 1 T131 2 T132 2 T176 1
all_values[2] auto[0] auto[0] auto[0] 66 1 T133 2 T177 1 T175 4
all_values[2] auto[0] auto[0] auto[1] 19 1 T131 2 T133 1 T173 2
all_values[2] auto[0] auto[1] auto[0] 48 1 T132 3 T176 2 T175 1
all_values[2] auto[0] auto[1] auto[1] 37 1 T131 2 T132 1 T133 1
all_values[2] auto[1] auto[0] auto[1] 67 1 T132 1 T133 3 T175 1
all_values[2] auto[1] auto[1] auto[1] 59 1 T131 3 T132 2 T173 1


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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