Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	99545886	1			T1	571892		T2	221689		T3	282
all_values[1]	99545886	1			T1	571892		T2	221689		T3	282
all_values[2]	99545886	1			T1	571892		T2	221689		T3	282

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

605832

1

T1

28

T2

22

T3

7

auto[1]

298031826

1

T1

171564

T2

665045

T3

839

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

297133701

1

T1

170511

T2

663345

T3

810

auto[1]

1503957

1

T1

10560

T2

1722

T3

36

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	231718	1			T1	3		T38	8		T8	1
all_values[0]	auto[0]	auto[1]	1924	1			T1	4		T38	8		T40	2
all_values[0]	auto[1]	auto[0]	98812849	1			T1	568369		T2	221115		T3	270
all_values[0]	auto[1]	auto[1]	499395	1			T1	3516		T2	574		T3	12
all_values[1]	auto[0]	auto[0]	177201	1			T1	12		T2	14		T23	482
all_values[1]	auto[0]	auto[1]	1443	1			T1	9		T2	5		T23	3
all_values[1]	auto[1]	auto[0]	98867366	1			T1	568360		T2	221101		T3	270
all_values[1]	auto[1]	auto[1]	499876	1			T1	3511		T2	569		T3	12
all_values[2]	auto[0]	auto[0]	192109	1			T2	2		T3	6		T7	279
all_values[2]	auto[0]	auto[1]	1437	1			T2	1		T3	1		T7	3
all_values[2]	auto[1]	auto[0]	98852458	1			T1	568372		T2	221113		T3	264
all_values[2]	auto[1]	auto[1]	499882	1			T1	3520		T2	573		T3	11