Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
348154 |
1 |
|
|
T1 |
4674 |
|
T2 |
2 |
|
T3 |
18 |
auto[1] |
332960 |
1 |
|
|
T2 |
778 |
|
T23 |
118 |
|
T7 |
150 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
170514 |
1 |
|
|
T1 |
1196 |
|
T2 |
192 |
|
T3 |
6 |
lower_val |
169477 |
1 |
|
|
T1 |
1158 |
|
T2 |
188 |
|
T3 |
2 |
zero_val |
1827 |
1 |
|
|
T1 |
3 |
|
T2 |
3 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
256564 |
1 |
|
|
T1 |
2312 |
|
T2 |
216 |
|
T3 |
12 |
lower_val |
257664 |
1 |
|
|
T1 |
2362 |
|
T2 |
218 |
|
T3 |
6 |
zero_val |
166886 |
1 |
|
|
T2 |
346 |
|
T23 |
50 |
|
T7 |
92 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
43518 |
1 |
|
|
T1 |
604 |
|
T3 |
3 |
|
T38 |
1 |
higher_val |
higher_val |
auto[1] |
20599 |
1 |
|
|
T2 |
55 |
|
T23 |
5 |
|
T7 |
10 |
higher_val |
lower_val |
auto[0] |
43263 |
1 |
|
|
T1 |
592 |
|
T3 |
3 |
|
T8 |
12 |
higher_val |
lower_val |
auto[1] |
21236 |
1 |
|
|
T2 |
61 |
|
T23 |
4 |
|
T7 |
7 |
higher_val |
zero_val |
auto[0] |
68 |
1 |
|
|
T48 |
1 |
|
T16 |
1 |
|
T79 |
1 |
higher_val |
zero_val |
auto[1] |
41830 |
1 |
|
|
T2 |
76 |
|
T23 |
11 |
|
T7 |
28 |
lower_val |
higher_val |
auto[0] |
43320 |
1 |
|
|
T1 |
585 |
|
T3 |
1 |
|
T8 |
10 |
lower_val |
higher_val |
auto[1] |
20777 |
1 |
|
|
T2 |
53 |
|
T23 |
12 |
|
T7 |
4 |
lower_val |
lower_val |
auto[0] |
43179 |
1 |
|
|
T1 |
573 |
|
T3 |
1 |
|
T8 |
14 |
lower_val |
lower_val |
auto[1] |
20783 |
1 |
|
|
T2 |
53 |
|
T23 |
15 |
|
T7 |
4 |
lower_val |
zero_val |
auto[0] |
70 |
1 |
|
|
T45 |
1 |
|
T73 |
1 |
|
T16 |
1 |
lower_val |
zero_val |
auto[1] |
41348 |
1 |
|
|
T2 |
82 |
|
T23 |
24 |
|
T7 |
20 |
zero_val |
higher_val |
auto[0] |
546 |
1 |
|
|
T1 |
2 |
|
T7 |
1 |
|
T38 |
1 |
zero_val |
higher_val |
auto[1] |
126 |
1 |
|
|
T2 |
2 |
|
T16 |
1 |
|
T72 |
2 |
zero_val |
lower_val |
auto[0] |
611 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
zero_val |
lower_val |
auto[1] |
123 |
1 |
|
|
T16 |
2 |
|
T72 |
2 |
|
T219 |
1 |
zero_val |
zero_val |
auto[0] |
234 |
1 |
|
|
T23 |
1 |
|
T45 |
1 |
|
T48 |
1 |
zero_val |
zero_val |
auto[1] |
187 |
1 |
|
|
T72 |
2 |
|
T219 |
7 |
|
T220 |
4 |