Group : kmac_env_pkg::kmac_env_cov::msg_len_cg
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Group : kmac_env_pkg::kmac_env_cov::msg_len_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv



Summary for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 15 0 15 100.00


Variables for Group kmac_env_pkg::kmac_env_cov::msg_len_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
msg_len 15 0 15 100.00 100 1 1 0


Summary for Variable msg_len

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 15 0 15 100.00


User Defined Bins for msg_len

Excluded/Illegal bins
NAMECOUNTSTATUS
remainder 10268 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
len_7501_10000 8674 1 T1 30 T2 17 T38 17
len_5001_7500 13845 1 T1 30 T2 17 T38 17
len_2501_5000 9098 1 T1 30 T2 17 T38 17
len_1025_2500 5293 1 T1 16 T2 10 T38 10
len_769_1024 6055 1 T1 4 T2 2 T23 15
len_513_768 6421 1 T1 2 T2 2 T23 12
len_257_512 20496 1 T1 244 T2 2 T23 16
len_0_256 254087 1 T1 1897 T2 290 T3 9
len_keccak_block_sizes[72] 713 1 T1 3 T2 2 T23 1
len_keccak_block_sizes[104] 619 1 T1 3 T2 2 T38 2
len_keccak_block_sizes[136] 515 1 T1 3 T2 2 T38 2
len_keccak_block_sizes[144] 424 1 T1 3 T2 2 T38 2
len_keccak_block_sizes[168] 322 1 T1 3 T40 3 T74 3
len_1 738 1 T1 3 T2 2 T38 2
len_0 1140 1 T1 3 T2 2 T38 2

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