Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	99545886	1			T1	571892		T2	221689		T3	282
all_pins[1]	99545886	1			T1	571892		T2	221689		T3	282
all_pins[2]	99545886	1			T1	571892		T2	221689		T3	282

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	297825678	1			T1	171216		T2	664493		T3	834
values[0x1]	811980	1			T1	3516		T2	574		T3	12
transitions[0x0=>0x1]	809953	1			T1	3516		T2	574		T3	12
transitions[0x1=>0x0]	809980	1			T1	3516		T2	574		T3	12

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	99046491	1			T1	568376		T2	221115		T3	270
all_pins[0]	values[0x1]	499395	1			T1	3516		T2	574		T3	12
all_pins[0]	transitions[0x0=>0x1]	499382	1			T1	3516		T2	574		T3	12
all_pins[0]	transitions[0x1=>0x0]	5397	1			T23	31		T7	15		T44	1
all_pins[1]	values[0x0]	99540476	1			T1	571892		T2	221689		T3	282
all_pins[1]	values[0x1]	5410	1			T23	31		T7	15		T44	1
all_pins[1]	transitions[0x0=>0x1]	5184	1			T23	31		T7	15		T44	1
all_pins[1]	transitions[0x1=>0x0]	306949	1			T9	8		T16	11148		T24	1886
all_pins[2]	values[0x0]	99238711	1			T1	571892		T2	221689		T3	282
all_pins[2]	values[0x1]	307175	1			T9	8		T16	11175		T24	1886
all_pins[2]	transitions[0x0=>0x1]	305387	1			T9	8		T16	11101		T24	1886
all_pins[2]	transitions[0x1=>0x0]	497634	1			T1	3516		T2	574		T3	12