Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	587	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5169	1			T23	12		T7	8		T8	2
len_601_800	11816	1			T23	23		T7	12		T8	11
len_401_600	7761	1			T23	13		T7	13		T8	5
len_201_400	16208	1			T23	4		T7	5		T8	5
len_65_200	72369	1			T1	685		T23	3		T7	5
len_min_for_xof_require_squeeze	991	1			T1	9		T40	10		T74	10
len_keccak_block_sizes[72]	740	1			T1	9		T40	5		T74	5
len_keccak_block_sizes[104]	749	1			T1	9		T40	5		T74	5
len_keccak_block_sizes[136]	734	1			T1	9		T40	5		T74	5
len_keccak_block_sizes[144]	284	1			T40	5		T74	5		T69	5
len_keccak_block_sizes[168]	282	1			T40	5		T73	1		T74	5
len_datapath_width	13723	1			T1	9		T3	3		T23	1
len_2_63	211215	1			T1	1643		T2	390		T3	6
len_1	37	1			T23	1		T16	1		T208	1