Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10294010 |
1 |
|
|
T1 |
27235 |
|
T2 |
2730 |
|
T3 |
96 |
auto[1] |
10293963 |
1 |
|
|
T1 |
27235 |
|
T2 |
2730 |
|
T3 |
96 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
20356083 |
1 |
|
|
T1 |
52796 |
|
T2 |
5460 |
|
T3 |
192 |
triple_byte_access |
77144 |
1 |
|
|
T1 |
558 |
|
T23 |
30 |
|
T7 |
30 |
halfword_access |
77922 |
1 |
|
|
T1 |
558 |
|
T23 |
32 |
|
T7 |
24 |
byte_access |
76824 |
1 |
|
|
T1 |
558 |
|
T23 |
40 |
|
T7 |
26 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10178065 |
1 |
|
|
T1 |
26398 |
|
T2 |
2730 |
|
T3 |
96 |
auto[0] |
triple_byte_access |
38572 |
1 |
|
|
T1 |
279 |
|
T23 |
15 |
|
T7 |
15 |
auto[0] |
halfword_access |
38961 |
1 |
|
|
T1 |
279 |
|
T23 |
16 |
|
T7 |
12 |
auto[0] |
byte_access |
38412 |
1 |
|
|
T1 |
279 |
|
T23 |
20 |
|
T7 |
13 |
auto[1] |
word_access |
10178018 |
1 |
|
|
T1 |
26398 |
|
T2 |
2730 |
|
T3 |
96 |
auto[1] |
triple_byte_access |
38572 |
1 |
|
|
T1 |
279 |
|
T23 |
15 |
|
T7 |
15 |
auto[1] |
halfword_access |
38961 |
1 |
|
|
T1 |
279 |
|
T23 |
16 |
|
T7 |
12 |
auto[1] |
byte_access |
38412 |
1 |
|
|
T1 |
279 |
|
T23 |
20 |
|
T7 |
13 |