Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	98752043	1			T1	73		T2	206230		T3	4157
all_values[1]	98752043	1			T1	73		T2	206230		T3	4157
all_values[2]	98752043	1			T1	73		T2	206230		T3	4157

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

504860

1

T1

60

T2

10

T3

428

auto[1]

295751269

1

T1

159

T2

618680

T3

12043

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

294764613

1

T1

180

T2

616962

T3

12354

auto[1]

1491516

1

T1

39

T2

1728

T3

117

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	168441	1			T1	48		T2	3		T31	1
all_values[0]	auto[0]	auto[1]	1952	1			T1	12		T2	4		T31	2
all_values[0]	auto[1]	auto[0]	98086430	1			T1	12		T2	205651		T3	4118
all_values[0]	auto[1]	auto[1]	495220	1			T1	1		T2	572		T3	39
all_values[1]	auto[0]	auto[0]	160264	1			T2	1		T3	372		T30	44
all_values[1]	auto[0]	auto[1]	1437	1			T2	2		T3	2		T30	2
all_values[1]	auto[1]	auto[0]	98094607	1			T1	60		T2	205653		T3	3746
all_values[1]	auto[1]	auto[1]	495735	1			T1	13		T2	574		T3	37
all_values[2]	auto[0]	auto[0]	171363	1			T3	53		T30	11		T32	4
all_values[2]	auto[0]	auto[1]	1403	1			T3	1		T30	1		T32	3
all_values[2]	auto[1]	auto[0]	98083508	1			T1	60		T2	205654		T3	4065
all_values[2]	auto[1]	auto[1]	495769	1			T1	13		T2	576		T3	38