Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
320164 |
1 |
|
|
T1 |
14 |
|
T2 |
2 |
|
T3 |
2 |
auto[1] |
354052 |
1 |
|
|
T2 |
746 |
|
T3 |
60 |
|
T7 |
10 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
168998 |
1 |
|
|
T1 |
4 |
|
T2 |
184 |
|
T3 |
7 |
lower_val |
167367 |
1 |
|
|
T1 |
5 |
|
T2 |
198 |
|
T3 |
12 |
zero_val |
1751 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
248860 |
1 |
|
|
T1 |
8 |
|
T2 |
200 |
|
T3 |
12 |
lower_val |
247616 |
1 |
|
|
T1 |
6 |
|
T2 |
196 |
|
T3 |
16 |
zero_val |
177740 |
1 |
|
|
T2 |
352 |
|
T3 |
34 |
|
T7 |
6 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
40098 |
1 |
|
|
T1 |
3 |
|
T30 |
46 |
|
T31 |
105 |
higher_val |
higher_val |
auto[1] |
22436 |
1 |
|
|
T2 |
56 |
|
T33 |
30 |
|
T35 |
32 |
higher_val |
lower_val |
auto[0] |
40017 |
1 |
|
|
T1 |
1 |
|
T30 |
51 |
|
T31 |
101 |
higher_val |
lower_val |
auto[1] |
22109 |
1 |
|
|
T2 |
40 |
|
T3 |
2 |
|
T33 |
25 |
higher_val |
zero_val |
auto[0] |
68 |
1 |
|
|
T36 |
1 |
|
T15 |
1 |
|
T191 |
1 |
higher_val |
zero_val |
auto[1] |
44270 |
1 |
|
|
T2 |
88 |
|
T3 |
5 |
|
T33 |
58 |
lower_val |
higher_val |
auto[0] |
39785 |
1 |
|
|
T1 |
3 |
|
T30 |
49 |
|
T31 |
83 |
lower_val |
higher_val |
auto[1] |
21919 |
1 |
|
|
T2 |
48 |
|
T3 |
3 |
|
T7 |
1 |
lower_val |
lower_val |
auto[0] |
39496 |
1 |
|
|
T1 |
2 |
|
T30 |
47 |
|
T31 |
83 |
lower_val |
lower_val |
auto[1] |
21870 |
1 |
|
|
T2 |
53 |
|
T3 |
3 |
|
T33 |
35 |
lower_val |
zero_val |
auto[0] |
89 |
1 |
|
|
T7 |
1 |
|
T17 |
1 |
|
T15 |
1 |
lower_val |
zero_val |
auto[1] |
44208 |
1 |
|
|
T2 |
97 |
|
T3 |
6 |
|
T33 |
79 |
zero_val |
higher_val |
auto[0] |
542 |
1 |
|
|
T31 |
1 |
|
T32 |
3 |
|
T7 |
1 |
zero_val |
higher_val |
auto[1] |
119 |
1 |
|
|
T15 |
1 |
|
T16 |
2 |
|
T192 |
1 |
zero_val |
lower_val |
auto[0] |
506 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T30 |
1 |
zero_val |
lower_val |
auto[1] |
132 |
1 |
|
|
T15 |
1 |
|
T16 |
1 |
|
T193 |
1 |
zero_val |
zero_val |
auto[0] |
246 |
1 |
|
|
T2 |
1 |
|
T7 |
1 |
|
T33 |
1 |
zero_val |
zero_val |
auto[1] |
206 |
1 |
|
|
T192 |
1 |
|
T193 |
1 |
|
T194 |
1 |