Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	98752043	1			T1	73		T2	206230		T3	4157
all_pins[1]	98752043	1			T1	73		T2	206230		T3	4157
all_pins[2]	98752043	1			T1	73		T2	206230		T3	4157

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	295517367	1			T1	218		T2	618118		T3	12415
values[0x1]	738762	1			T1	1		T2	572		T3	56
transitions[0x0=>0x1]	737042	1			T1	1		T2	572		T3	56
transitions[0x1=>0x0]	737058	1			T1	1		T2	572		T3	56

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	98256823	1			T1	72		T2	205658		T3	4118
all_pins[0]	values[0x1]	495220	1			T1	1		T2	572		T3	39
all_pins[0]	transitions[0x0=>0x1]	495211	1			T1	1		T2	572		T3	39
all_pins[0]	transitions[0x1=>0x0]	5333	1			T3	6		T7	2		T59	21
all_pins[1]	values[0x0]	98746701	1			T1	73		T2	206230		T3	4151
all_pins[1]	values[0x1]	5342	1			T3	6		T7	2		T59	21
all_pins[1]	transitions[0x0=>0x1]	5038	1			T3	6		T7	2		T59	21
all_pins[1]	transitions[0x1=>0x0]	237896	1			T3	11		T7	375		T60	16
all_pins[2]	values[0x0]	98513843	1			T1	73		T2	206230		T3	4146
all_pins[2]	values[0x1]	238200	1			T3	11		T7	375		T60	16
all_pins[2]	transitions[0x0=>0x1]	236793	1			T3	11		T7	373		T60	16
all_pins[2]	transitions[0x1=>0x0]	493829	1			T1	1		T2	572		T3	39