Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	640	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5097	1			T3	1		T30	28		T7	7
len_601_800	11421	1			T3	12		T30	70		T7	17
len_401_600	7605	1			T3	4		T30	51		T7	9
len_201_400	15963	1			T3	2		T30	19		T7	9
len_65_200	72057	1			T1	5		T30	12		T7	6
len_min_for_xof_require_squeeze	973	1			T34	10		T60	1		T15	2
len_keccak_block_sizes[72]	728	1			T34	5		T195	5		T191	1
len_keccak_block_sizes[104]	736	1			T34	5		T195	5		T193	9
len_keccak_block_sizes[136]	754	1			T7	1		T34	5		T150	1
len_keccak_block_sizes[144]	277	1			T34	5		T8	1		T195	5
len_keccak_block_sizes[168]	265	1			T34	5		T195	5		T194	5
len_datapath_width	13947	1			T1	1		T33	246		T34	5
len_2_63	208947	1			T1	1		T2	374		T3	5
len_1	47	1			T196	1		T116	1		T197	2