Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	98844403	1			T1	563567		T15	559051		T16	4009
all_values[1]	98844403	1			T1	563567		T15	559051		T16	4009
all_values[2]	98844403	1			T1	563567		T15	559051		T16	4009

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

493353

1

T1

14

T15

14

T16

516

auto[1]

296039856

1

T1

169068

T15

167713

T16

11511

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

295016568

1

T1

168031

T15

166659

T16

11907

auto[1]

1516641

1

T1

10389

T15

10557

T16

120

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	190255	1			T1	3		T15	3		T16	192
all_values[0]	auto[0]	auto[1]	1983	1			T1	4		T15	4		T16	2
all_values[0]	auto[1]	auto[0]	98148601	1			T1	560101		T15	555529		T16	3777
all_values[0]	auto[1]	auto[1]	503564	1			T1	3459		T15	3515		T16	38
all_values[1]	auto[0]	auto[0]	137830	1			T1	3		T16	319		T33	5
all_values[1]	auto[0]	auto[1]	1457	1			T1	4		T16	3		T33	2
all_values[1]	auto[1]	auto[0]	98201026	1			T1	560101		T15	555532		T16	3650
all_values[1]	auto[1]	auto[1]	504090	1			T1	3459		T15	3519		T16	37
all_values[2]	auto[0]	auto[0]	160327	1			T15	3		T33	5		T7	17
all_values[2]	auto[0]	auto[1]	1501	1			T15	4		T33	2		T7	2
all_values[2]	auto[1]	auto[0]	98178529	1			T1	560104		T15	555529		T16	3969
all_values[2]	auto[1]	auto[1]	504046	1			T1	3463		T15	3515		T16	40