Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	98844403	1			T1	563567		T15	559051		T16	4009
all_pins[1]	98844403	1			T1	563567		T15	559051		T16	4009
all_pins[2]	98844403	1			T1	563567		T15	559051		T16	4009

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	295692198	1			T1	168724		T15	167363		T16	11989
values[0x1]	841011	1			T1	3459		T15	3515		T16	38
transitions[0x0=>0x1]	838755	1			T1	3459		T15	3515		T16	38
transitions[0x1=>0x0]	838774	1			T1	3459		T15	3515		T16	38

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	98340839	1			T1	560108		T15	555536		T16	3971
all_pins[0]	values[0x1]	503564	1			T1	3459		T15	3515		T16	38
all_pins[0]	transitions[0x0=>0x1]	503551	1			T1	3459		T15	3515		T16	38
all_pins[0]	transitions[0x1=>0x0]	5278	1			T7	47		T34	2		T37	117
all_pins[1]	values[0x0]	98839112	1			T1	563567		T15	559051		T16	4009
all_pins[1]	values[0x1]	5291	1			T7	47		T34	2		T37	117
all_pins[1]	transitions[0x0=>0x1]	5088	1			T7	45		T34	2		T37	117
all_pins[1]	transitions[0x1=>0x0]	331953	1			T7	2441		T13	7363		T41	1598
all_pins[2]	values[0x0]	98512247	1			T1	563567		T15	559051		T16	4009
all_pins[2]	values[0x1]	332156	1			T7	2443		T13	7374		T41	1598
all_pins[2]	transitions[0x0=>0x1]	330116	1			T7	2427		T13	7326		T41	1598
all_pins[2]	transitions[0x1=>0x0]	501543	1			T1	3459		T15	3515		T16	38