Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10455391 |
1 |
|
|
T1 |
27235 |
|
T15 |
27235 |
|
T16 |
3533 |
auto[1] |
10455391 |
1 |
|
|
T1 |
27235 |
|
T15 |
27235 |
|
T16 |
3533 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
20675354 |
1 |
|
|
T1 |
52796 |
|
T15 |
52796 |
|
T16 |
7026 |
triple_byte_access |
78226 |
1 |
|
|
T1 |
558 |
|
T15 |
558 |
|
T16 |
10 |
halfword_access |
78770 |
1 |
|
|
T1 |
558 |
|
T15 |
558 |
|
T16 |
22 |
byte_access |
78432 |
1 |
|
|
T1 |
558 |
|
T15 |
558 |
|
T16 |
8 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10337677 |
1 |
|
|
T1 |
26398 |
|
T15 |
26398 |
|
T16 |
3513 |
auto[0] |
triple_byte_access |
39113 |
1 |
|
|
T1 |
279 |
|
T15 |
279 |
|
T16 |
5 |
auto[0] |
halfword_access |
39385 |
1 |
|
|
T1 |
279 |
|
T15 |
279 |
|
T16 |
11 |
auto[0] |
byte_access |
39216 |
1 |
|
|
T1 |
279 |
|
T15 |
279 |
|
T16 |
4 |
auto[1] |
word_access |
10337677 |
1 |
|
|
T1 |
26398 |
|
T15 |
26398 |
|
T16 |
3513 |
auto[1] |
triple_byte_access |
39113 |
1 |
|
|
T1 |
279 |
|
T15 |
279 |
|
T16 |
5 |
auto[1] |
halfword_access |
39385 |
1 |
|
|
T1 |
279 |
|
T15 |
279 |
|
T16 |
11 |
auto[1] |
byte_access |
39216 |
1 |
|
|
T1 |
279 |
|
T15 |
279 |
|
T16 |
4 |