Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	98897328	1			T1	35409		T2	153343		T3	272
all_values[1]	98897328	1			T1	35409		T2	153343		T3	272
all_values[2]	98897328	1			T1	35409		T2	153343		T3	272

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

599808

1

T1

3143

T2

1718

T3

14

auto[1]

296092176

1

T1

103084

T2

458311

T3

802

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

295167117

1

T1

105909

T2

459552

T3

774

auto[1]

1524867

1

T1

318

T2

477

T3

42

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	177033	1			T1	191		T32	55		T35	5
all_values[0]	auto[0]	auto[1]	1957	1			T1	4		T32	8		T35	6
all_values[0]	auto[1]	auto[0]	98212006	1			T1	35112		T2	153184		T3	258
all_values[0]	auto[1]	auto[1]	506332	1			T1	102		T2	159		T3	14
all_values[1]	auto[0]	auto[0]	189528	1			T2	1716		T32	16		T33	2
all_values[1]	auto[0]	auto[1]	1517	1			T2	2		T32	2		T33	1
all_values[1]	auto[1]	auto[0]	98199511	1			T1	35303		T2	151468		T3	258
all_values[1]	auto[1]	auto[1]	506772	1			T1	106		T2	157		T3	14
all_values[2]	auto[0]	auto[0]	228074	1			T1	2942		T3	11		T32	129
all_values[2]	auto[0]	auto[1]	1699	1			T1	6		T3	3		T32	12
all_values[2]	auto[1]	auto[0]	98160965	1			T1	32361		T2	153184		T3	247
all_values[2]	auto[1]	auto[1]	506590	1			T1	100		T2	159		T3	11