Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
390514 |
1 |
|
|
T1 |
120 |
|
T2 |
210 |
|
T3 |
2 |
auto[1] |
300530 |
1 |
|
|
T1 |
36 |
|
T3 |
16 |
|
T32 |
280 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
173002 |
1 |
|
|
T1 |
52 |
|
T2 |
53 |
|
T3 |
6 |
lower_val |
170999 |
1 |
|
|
T1 |
36 |
|
T2 |
58 |
|
T3 |
8 |
zero_val |
1763 |
1 |
|
|
T1 |
4 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
269706 |
1 |
|
|
T1 |
68 |
|
T2 |
104 |
|
T3 |
4 |
lower_val |
270030 |
1 |
|
|
T1 |
68 |
|
T2 |
106 |
|
T3 |
4 |
zero_val |
151308 |
1 |
|
|
T1 |
20 |
|
T3 |
10 |
|
T32 |
132 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
48854 |
1 |
|
|
T1 |
24 |
|
T2 |
27 |
|
T12 |
1 |
higher_val |
higher_val |
auto[1] |
18709 |
1 |
|
|
T1 |
1 |
|
T3 |
2 |
|
T32 |
19 |
higher_val |
lower_val |
auto[0] |
48820 |
1 |
|
|
T1 |
20 |
|
T2 |
26 |
|
T33 |
1 |
higher_val |
lower_val |
auto[1] |
18725 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T32 |
15 |
higher_val |
zero_val |
auto[0] |
95 |
1 |
|
|
T1 |
1 |
|
T35 |
1 |
|
T39 |
1 |
higher_val |
zero_val |
auto[1] |
37799 |
1 |
|
|
T1 |
5 |
|
T3 |
3 |
|
T32 |
32 |
lower_val |
higher_val |
auto[0] |
48090 |
1 |
|
|
T1 |
14 |
|
T2 |
28 |
|
T34 |
96 |
lower_val |
higher_val |
auto[1] |
18546 |
1 |
|
|
T1 |
2 |
|
T3 |
1 |
|
T32 |
16 |
lower_val |
lower_val |
auto[0] |
48059 |
1 |
|
|
T1 |
14 |
|
T2 |
30 |
|
T3 |
1 |
lower_val |
lower_val |
auto[1] |
18749 |
1 |
|
|
T1 |
4 |
|
T3 |
1 |
|
T32 |
18 |
lower_val |
zero_val |
auto[0] |
74 |
1 |
|
|
T35 |
1 |
|
T113 |
1 |
|
T16 |
1 |
lower_val |
zero_val |
auto[1] |
37481 |
1 |
|
|
T1 |
2 |
|
T3 |
5 |
|
T32 |
38 |
zero_val |
higher_val |
auto[0] |
547 |
1 |
|
|
T2 |
1 |
|
T12 |
1 |
|
T34 |
1 |
zero_val |
higher_val |
auto[1] |
127 |
1 |
|
|
T1 |
1 |
|
T15 |
1 |
|
T17 |
1 |
zero_val |
lower_val |
auto[0] |
552 |
1 |
|
|
T1 |
3 |
|
T3 |
1 |
|
T32 |
1 |
zero_val |
lower_val |
auto[1] |
105 |
1 |
|
|
T15 |
2 |
|
T115 |
1 |
|
T17 |
1 |
zero_val |
zero_val |
auto[0] |
265 |
1 |
|
|
T30 |
1 |
|
T39 |
1 |
|
T19 |
1 |
zero_val |
zero_val |
auto[1] |
167 |
1 |
|
|
T15 |
2 |
|
T115 |
1 |
|
T17 |
1 |