Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	98897328	1			T1	35409		T2	153343		T3	272
all_pins[1]	98897328	1			T1	35409		T2	153343		T3	272
all_pins[2]	98897328	1			T1	35409		T2	153343		T3	272

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	295890963	1			T1	106125		T2	459801		T3	802
values[0x1]	801021	1			T1	102		T2	228		T3	14
transitions[0x0=>0x1]	799066	1			T1	102		T2	228		T3	14
transitions[0x1=>0x0]	799097	1			T1	102		T2	228		T3	14

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	98390996	1			T1	35307		T2	153184		T3	258
all_pins[0]	values[0x1]	506332	1			T1	102		T2	159		T3	14
all_pins[0]	transitions[0x0=>0x1]	506316	1			T1	102		T2	159		T3	14
all_pins[0]	transitions[0x1=>0x0]	5328	1			T2	69		T7	11		T49	5
all_pins[1]	values[0x0]	98891984	1			T1	35409		T2	153274		T3	272
all_pins[1]	values[0x1]	5344	1			T2	69		T7	11		T49	5
all_pins[1]	transitions[0x0=>0x1]	5147	1			T2	69		T7	11		T49	5
all_pins[1]	transitions[0x1=>0x0]	289148	1			T20	722		T15	8103		T16	17780
all_pins[2]	values[0x0]	98607983	1			T1	35409		T2	153343		T3	272
all_pins[2]	values[0x1]	289345	1			T20	722		T15	8122		T16	17780
all_pins[2]	transitions[0x0=>0x1]	287603	1			T20	721		T15	8068		T16	17658
all_pins[2]	transitions[0x1=>0x0]	504621	1			T1	102		T2	159		T3	14