Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10727263 |
1 |
|
|
T1 |
8691 |
|
T2 |
18160 |
|
T3 |
96 |
auto[1] |
10727181 |
1 |
|
|
T1 |
8691 |
|
T2 |
18160 |
|
T3 |
96 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
21215834 |
1 |
|
|
T1 |
17302 |
|
T2 |
36178 |
|
T3 |
192 |
triple_byte_access |
79212 |
1 |
|
|
T1 |
28 |
|
T2 |
42 |
|
T32 |
64 |
halfword_access |
79968 |
1 |
|
|
T1 |
24 |
|
T2 |
48 |
|
T32 |
66 |
byte_access |
79430 |
1 |
|
|
T1 |
28 |
|
T2 |
52 |
|
T32 |
80 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10607958 |
1 |
|
|
T1 |
8651 |
|
T2 |
18089 |
|
T3 |
96 |
auto[0] |
triple_byte_access |
39606 |
1 |
|
|
T1 |
14 |
|
T2 |
21 |
|
T32 |
32 |
auto[0] |
halfword_access |
39984 |
1 |
|
|
T1 |
12 |
|
T2 |
24 |
|
T32 |
33 |
auto[0] |
byte_access |
39715 |
1 |
|
|
T1 |
14 |
|
T2 |
26 |
|
T32 |
40 |
auto[1] |
word_access |
10607876 |
1 |
|
|
T1 |
8651 |
|
T2 |
18089 |
|
T3 |
96 |
auto[1] |
triple_byte_access |
39606 |
1 |
|
|
T1 |
14 |
|
T2 |
21 |
|
T32 |
32 |
auto[1] |
halfword_access |
39984 |
1 |
|
|
T1 |
12 |
|
T2 |
24 |
|
T32 |
33 |
auto[1] |
byte_access |
39715 |
1 |
|
|
T1 |
14 |
|
T2 |
26 |
|
T32 |
40 |