Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	98958812	1			T2	2094		T3	304		T18	1619
all_values[1]	98958812	1			T2	2094		T3	304		T18	1619
all_values[2]	98958812	1			T2	2094		T3	304		T18	1619

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

536026

1

T3

6

T18

29

T35

3

auto[1]

296340410

1

T2

6282

T3

906

T18

4828

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

295371435

1

T2

6228

T3

873

T18

4158

auto[1]

1505001

1

T2

54

T3

39

T18

699

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	160183	1			T18	8		T42	1		T7	1745
all_values[0]	auto[0]	auto[1]	1899	1			T18	4		T42	2		T7	24
all_values[0]	auto[1]	auto[0]	98296962	1			T2	2076		T3	291		T18	1378
all_values[0]	auto[1]	auto[1]	499768	1			T2	18		T3	13		T18	229
all_values[1]	auto[0]	auto[0]	203271	1			T3	5		T18	3		T36	81
all_values[1]	auto[0]	auto[1]	1477	1			T3	1		T18	2		T36	6
all_values[1]	auto[1]	auto[0]	98253874	1			T2	2076		T3	286		T18	1383
all_values[1]	auto[1]	auto[1]	500190	1			T2	18		T3	12		T18	231
all_values[2]	auto[0]	auto[0]	167818	1			T18	8		T35	2		T39	8
all_values[2]	auto[0]	auto[1]	1378	1			T18	4		T35	1		T39	1
all_values[2]	auto[1]	auto[0]	98289327	1			T2	2076		T3	291		T18	1378
all_values[2]	auto[1]	auto[1]	500289	1			T2	18		T3	13		T18	229