Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
326272 |
1 |
|
|
T2 |
28 |
|
T3 |
2 |
|
T18 |
2 |
auto[1] |
354898 |
1 |
|
|
T3 |
16 |
|
T18 |
310 |
|
T35 |
4528 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
171090 |
1 |
|
|
T2 |
12 |
|
T3 |
1 |
|
T18 |
60 |
lower_val |
168802 |
1 |
|
|
T2 |
6 |
|
T3 |
2 |
|
T18 |
93 |
zero_val |
1763 |
1 |
|
|
T2 |
1 |
|
T3 |
1 |
|
T18 |
3 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
251842 |
1 |
|
|
T2 |
16 |
|
T3 |
6 |
|
T18 |
88 |
lower_val |
251080 |
1 |
|
|
T2 |
12 |
|
T3 |
6 |
|
T18 |
106 |
zero_val |
178248 |
1 |
|
|
T3 |
6 |
|
T18 |
118 |
|
T35 |
2218 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
40921 |
1 |
|
|
T2 |
7 |
|
T36 |
3 |
|
T42 |
620 |
higher_val |
higher_val |
auto[1] |
22413 |
1 |
|
|
T3 |
1 |
|
T18 |
18 |
|
T35 |
301 |
higher_val |
lower_val |
auto[0] |
41130 |
1 |
|
|
T2 |
5 |
|
T35 |
1 |
|
T36 |
1 |
higher_val |
lower_val |
auto[1] |
22052 |
1 |
|
|
T18 |
24 |
|
T35 |
289 |
|
T39 |
1 |
higher_val |
zero_val |
auto[0] |
72 |
1 |
|
|
T46 |
1 |
|
T186 |
1 |
|
T73 |
1 |
higher_val |
zero_val |
auto[1] |
44502 |
1 |
|
|
T18 |
18 |
|
T35 |
525 |
|
T39 |
2 |
lower_val |
higher_val |
auto[0] |
40660 |
1 |
|
|
T2 |
4 |
|
T36 |
4 |
|
T42 |
597 |
lower_val |
higher_val |
auto[1] |
21791 |
1 |
|
|
T3 |
1 |
|
T18 |
24 |
|
T35 |
281 |
lower_val |
lower_val |
auto[0] |
40089 |
1 |
|
|
T2 |
2 |
|
T18 |
1 |
|
T36 |
4 |
lower_val |
lower_val |
auto[1] |
21907 |
1 |
|
|
T3 |
1 |
|
T18 |
40 |
|
T35 |
292 |
lower_val |
zero_val |
auto[0] |
72 |
1 |
|
|
T7 |
1 |
|
T195 |
1 |
|
T196 |
1 |
lower_val |
zero_val |
auto[1] |
44283 |
1 |
|
|
T18 |
28 |
|
T35 |
571 |
|
T39 |
4 |
zero_val |
higher_val |
auto[0] |
548 |
1 |
|
|
T2 |
1 |
|
T36 |
1 |
|
T7 |
2 |
zero_val |
higher_val |
auto[1] |
132 |
1 |
|
|
T18 |
2 |
|
T35 |
3 |
|
T7 |
1 |
zero_val |
lower_val |
auto[0] |
522 |
1 |
|
|
T3 |
1 |
|
T18 |
1 |
|
T35 |
1 |
zero_val |
lower_val |
auto[1] |
114 |
1 |
|
|
T35 |
1 |
|
T7 |
1 |
|
T8 |
1 |
zero_val |
zero_val |
auto[0] |
247 |
1 |
|
|
T40 |
1 |
|
T7 |
1 |
|
T8 |
1 |
zero_val |
zero_val |
auto[1] |
200 |
1 |
|
|
T35 |
4 |
|
T7 |
3 |
|
T8 |
1 |