Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	98958812	1			T2	2094		T3	304		T18	1619
all_pins[1]	98958812	1			T2	2094		T3	304		T18	1619
all_pins[2]	98958812	1			T2	2094		T3	304		T18	1619

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	296047157	1			T2	6264		T3	899		T18	4628
values[0x1]	829279	1			T2	18		T3	13		T18	229
transitions[0x0=>0x1]	827017	1			T2	18		T3	13		T18	229
transitions[0x1=>0x0]	827041	1			T2	18		T3	13		T18	229

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	98459044	1			T2	2076		T3	291		T18	1390
all_pins[0]	values[0x1]	499768	1			T2	18		T3	13		T18	229
all_pins[0]	transitions[0x0=>0x1]	499749	1			T2	18		T3	13		T18	229
all_pins[0]	transitions[0x1=>0x0]	6631	1			T39	1		T7	102		T8	35
all_pins[1]	values[0x0]	98952162	1			T2	2094		T3	304		T18	1619
all_pins[1]	values[0x1]	6650	1			T39	1		T7	102		T8	35
all_pins[1]	transitions[0x0=>0x1]	6349	1			T39	1		T7	83		T8	35
all_pins[1]	transitions[0x1=>0x0]	322560	1			T7	9580		T20	400		T21	206
all_pins[2]	values[0x0]	98635951	1			T2	2094		T3	304		T18	1619
all_pins[2]	values[0x1]	322861	1			T7	9599		T20	400		T21	206
all_pins[2]	transitions[0x0=>0x1]	320919	1			T7	9549		T20	400		T21	206
all_pins[2]	transitions[0x1=>0x0]	497850	1			T2	18		T3	13		T18	229