Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	596	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5053	1			T2	2		T7	45		T8	9
len_601_800	11518	1			T2	5		T7	99		T8	37
len_401_600	7515	1			T2	4		T7	70		T8	19
len_201_400	15903	1			T2	1		T35	251		T7	28
len_65_200	72678	1			T18	86		T35	680		T42	685
len_min_for_xof_require_squeeze	995	1			T35	10		T42	9		T7	1
len_keccak_block_sizes[72]	746	1			T35	5		T42	9		T70	9
len_keccak_block_sizes[104]	734	1			T18	1		T35	5		T42	9
len_keccak_block_sizes[136]	742	1			T18	2		T35	5		T42	9
len_keccak_block_sizes[144]	275	1			T18	1		T35	5		T73	5
len_keccak_block_sizes[168]	278	1			T35	5		T52	1		T73	5
len_datapath_width	13973	1			T3	3		T18	3		T35	5
len_2_63	211896	1			T2	1		T3	6		T18	65
len_1	47	1			T18	2		T74	1		T197	1