Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10160583 |
1 |
|
|
T2 |
2546 |
|
T3 |
96 |
|
T18 |
5568 |
auto[1] |
10160545 |
1 |
|
|
T2 |
2546 |
|
T3 |
96 |
|
T18 |
5568 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
20089722 |
1 |
|
|
T2 |
5076 |
|
T3 |
192 |
|
T18 |
10922 |
triple_byte_access |
76664 |
1 |
|
|
T2 |
2 |
|
T18 |
56 |
|
T35 |
620 |
halfword_access |
77554 |
1 |
|
|
T2 |
4 |
|
T18 |
86 |
|
T35 |
632 |
byte_access |
77188 |
1 |
|
|
T2 |
10 |
|
T18 |
72 |
|
T35 |
620 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10044880 |
1 |
|
|
T2 |
2538 |
|
T3 |
96 |
|
T18 |
5461 |
auto[0] |
triple_byte_access |
38332 |
1 |
|
|
T2 |
1 |
|
T18 |
28 |
|
T35 |
310 |
auto[0] |
halfword_access |
38777 |
1 |
|
|
T2 |
2 |
|
T18 |
43 |
|
T35 |
316 |
auto[0] |
byte_access |
38594 |
1 |
|
|
T2 |
5 |
|
T18 |
36 |
|
T35 |
310 |
auto[1] |
word_access |
10044842 |
1 |
|
|
T2 |
2538 |
|
T3 |
96 |
|
T18 |
5461 |
auto[1] |
triple_byte_access |
38332 |
1 |
|
|
T2 |
1 |
|
T18 |
28 |
|
T35 |
310 |
auto[1] |
halfword_access |
38777 |
1 |
|
|
T2 |
2 |
|
T18 |
43 |
|
T35 |
316 |
auto[1] |
byte_access |
38594 |
1 |
|
|
T2 |
5 |
|
T18 |
36 |
|
T35 |
310 |