Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	100665580	1			T1	2195		T2	224820		T3	272287
all_values[1]	100665580	1			T1	2195		T2	224820		T3	272287
all_values[2]	100665580	1			T1	2195		T2	224820		T3	272287

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

523744

1

T1

584

T2

43

T3

10200

auto[1]

301472996

1

T1

6001

T2

674417

T3

806661

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

300476589

1

T1

6519

T2

672687

T3

816114

auto[1]

1520151

1

T1

66

T2

1773

T3

747

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	183119	1			T1	193		T2	14		T35	1
all_values[0]	auto[0]	auto[1]	2072	1			T1	2		T2	12		T35	2
all_values[0]	auto[1]	auto[0]	99975744	1			T1	1980		T2	224215		T3	272038
all_values[0]	auto[1]	auto[1]	504645	1			T1	20		T2	579		T3	249
all_values[1]	auto[0]	auto[0]	185276	1			T1	192		T2	9		T3	10192
all_values[1]	auto[0]	auto[1]	1412	1			T1	2		T2	8		T3	8
all_values[1]	auto[1]	auto[0]	99973587	1			T1	1981		T2	224220		T3	261846
all_values[1]	auto[1]	auto[1]	505305	1			T1	20		T2	583		T3	241
all_values[2]	auto[0]	auto[0]	150401	1			T1	193		T34	2		T33	60
all_values[2]	auto[0]	auto[1]	1464	1			T1	2		T34	1		T33	3
all_values[2]	auto[1]	auto[0]	100008462	1			T1	1980		T2	224229		T3	272038
all_values[2]	auto[1]	auto[1]	505253	1			T1	20		T2	591		T3	249