Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msgfifo_level_cg

Group : kmac_env_pkg::kmac_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

---

Summary for Group kmac_env_pkg::kmac_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hash_mode	3	0	3	100.00	100	1	1	0
kmac_mode	2	0	2	100.00	100	1	1	2
msgfifo_depth	11	0	11	100.00	100	1	1	0
msgfifo_empty	2	0	2	100.00	100	1	1	2
msgfifo_full	2	0	2	100.00	100	1	1	2

Summary for Variable hash_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for hash_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
cshake	16004201	1			T1	1694		T3	232918		T33	47065
shake	56834718	1			T1	1068		T3	66618		T33	15743
sha3	34833416	1			T1	1		T2	224039		T3	3986

---

Summary for Variable kmac_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_mode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

91667047

1

T1

1071

T2

224039

T3

70604

auto[1]

16005288

1

T1

1692

T3

232918

T33

47065

---

Summary for Variable msgfifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for msgfifo_depth

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
depth[0x00]	93279193	1			T1	2692		T2	223574		T3	230487
depth[0x01]	3508229	1			T1	60		T2	465		T3	14845
depth[0x02]	2906475	1			T1	10		T3	15637		T34	27
depth[0x03]	2702305	1			T1	1		T3	14953		T33	7299
depth[0x04]	2418738	1			T3	14401		T33	5297		T36	11657
depth[0x05]	1333918	1			T3	8104		T33	3959		T36	5750
depth[0x06]	309971	1			T3	1531		T33	2359		T36	1
depth[0x07]	245172	1			T3	280		T33	1001		T37	486
depth[0x08]	237872	1			T3	383		T33	243		T37	161
depth[0x09]	222647	1			T3	269		T33	113		T37	78
depth[0x0a]	507815	1			T3	2632		T33	1825		T37	967

---

Summary for Variable msgfifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for msgfifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

14393142

1

T1

71

T2

465

T3

73035

auto[1]

93279193

1

T1

2692

T2

223574

T3

230487

---

Summary for Variable msgfifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for msgfifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

107164520

1

T1

2763

T2

224039

T3

300890

auto[1]

507815

1

T3

2632

T33

1825

T37

967