Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	100665580	1			T1	2195		T2	224820		T3	272287
all_pins[1]	100665580	1			T1	2195		T2	224820		T3	272287
all_pins[2]	100665580	1			T1	2195		T2	224820		T3	272287

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	301212067	1			T1	6565		T2	673881		T3	816539
values[0x1]	784673	1			T1	20		T2	579		T3	322
transitions[0x0=>0x1]	782742	1			T1	20		T2	579		T3	322
transitions[0x1=>0x0]	782764	1			T1	20		T2	579		T3	322

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	100160935	1			T1	2175		T2	224241		T3	272038
all_pins[0]	values[0x1]	504645	1			T1	20		T2	579		T3	249
all_pins[0]	transitions[0x0=>0x1]	504634	1			T1	20		T2	579		T3	249
all_pins[0]	transitions[0x1=>0x0]	5707	1			T3	73		T33	3		T7	15
all_pins[1]	values[0x0]	100659862	1			T1	2195		T2	224820		T3	272214
all_pins[1]	values[0x1]	5718	1			T3	73		T33	3		T7	15
all_pins[1]	transitions[0x0=>0x1]	5478	1			T3	73		T33	3		T7	15
all_pins[1]	transitions[0x1=>0x0]	274070	1			T9	218		T41	13		T39	637
all_pins[2]	values[0x0]	100391270	1			T1	2195		T2	224820		T3	272287
all_pins[2]	values[0x1]	274310	1			T9	218		T41	13		T39	637
all_pins[2]	transitions[0x0=>0x1]	272630	1			T9	218		T41	13		T39	637
all_pins[2]	transitions[0x1=>0x0]	502987	1			T1	20		T2	579		T3	249