Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10793141 |
1 |
|
|
T1 |
2613 |
|
T2 |
2730 |
|
T3 |
27572 |
auto[1] |
10793096 |
1 |
|
|
T1 |
2613 |
|
T2 |
2730 |
|
T3 |
27572 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
21348361 |
1 |
|
|
T1 |
5204 |
|
T2 |
5460 |
|
T3 |
54894 |
triple_byte_access |
78824 |
1 |
|
|
T1 |
6 |
|
T3 |
86 |
|
T33 |
106 |
halfword_access |
79606 |
1 |
|
|
T1 |
10 |
|
T3 |
68 |
|
T33 |
80 |
byte_access |
79446 |
1 |
|
|
T1 |
6 |
|
T3 |
96 |
|
T33 |
74 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10674203 |
1 |
|
|
T1 |
2602 |
|
T2 |
2730 |
|
T3 |
27447 |
auto[0] |
triple_byte_access |
39412 |
1 |
|
|
T1 |
3 |
|
T3 |
43 |
|
T33 |
53 |
auto[0] |
halfword_access |
39803 |
1 |
|
|
T1 |
5 |
|
T3 |
34 |
|
T33 |
40 |
auto[0] |
byte_access |
39723 |
1 |
|
|
T1 |
3 |
|
T3 |
48 |
|
T33 |
37 |
auto[1] |
word_access |
10674158 |
1 |
|
|
T1 |
2602 |
|
T2 |
2730 |
|
T3 |
27447 |
auto[1] |
triple_byte_access |
39412 |
1 |
|
|
T1 |
3 |
|
T3 |
43 |
|
T33 |
53 |
auto[1] |
halfword_access |
39803 |
1 |
|
|
T1 |
5 |
|
T3 |
34 |
|
T33 |
40 |
auto[1] |
byte_access |
39723 |
1 |
|
|
T1 |
3 |
|
T3 |
48 |
|
T33 |
37 |