Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	98321593	1			T1	59376		T2	12519		T3	213691
all_values[1]	98321593	1			T1	59376		T2	12519		T3	213691
all_values[2]	98321593	1			T1	59376		T2	12519		T3	213691

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

479658

1

T1

1447

T2

709

T3

18

auto[1]

294485121

1

T1

176681

T2

36848

T3

641055

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

293459487

1

T1

177144

T2

37209

T3

639450

auto[1]

1505292

1

T1

984

T2

348

T3

1623

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	134902	1			T1	1104		T2	435		T3	3
all_values[0]	auto[0]	auto[1]	1979	1			T1	18		T2	6		T3	4
all_values[0]	auto[1]	auto[0]	97684927	1			T1	57944		T2	11968		T3	213147
all_values[0]	auto[1]	auto[1]	499785	1			T1	310		T2	110		T3	537
all_values[1]	auto[0]	auto[0]	182480	1			T1	199		T2	266		T3	6
all_values[1]	auto[0]	auto[1]	1564	1			T1	7		T2	2		T3	5
all_values[1]	auto[1]	auto[0]	97637349	1			T1	58849		T2	12137		T3	213144
all_values[1]	auto[1]	auto[1]	500200	1			T1	321		T2	114		T3	536
all_values[2]	auto[0]	auto[0]	157095	1			T1	115		T32	4		T18	181
all_values[2]	auto[0]	auto[1]	1638	1			T1	4		T32	2		T18	2
all_values[2]	auto[1]	auto[0]	97662734	1			T1	58933		T2	12403		T3	213150
all_values[2]	auto[1]	auto[1]	500126	1			T1	324		T2	116		T3	541