Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
298842 |
1 |
|
|
T1 |
254 |
|
T2 |
258 |
|
T3 |
2 |
auto[1] |
384446 |
1 |
|
|
T1 |
206 |
|
T3 |
746 |
|
T34 |
244 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
171506 |
1 |
|
|
T1 |
115 |
|
T2 |
56 |
|
T3 |
199 |
lower_val |
169241 |
1 |
|
|
T1 |
125 |
|
T2 |
78 |
|
T3 |
184 |
zero_val |
1814 |
1 |
|
|
T1 |
7 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
245832 |
1 |
|
|
T1 |
166 |
|
T2 |
110 |
|
T3 |
178 |
lower_val |
245414 |
1 |
|
|
T1 |
204 |
|
T2 |
148 |
|
T3 |
178 |
zero_val |
192042 |
1 |
|
|
T1 |
90 |
|
T3 |
392 |
|
T34 |
94 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
37588 |
1 |
|
|
T1 |
29 |
|
T2 |
30 |
|
T32 |
2 |
higher_val |
higher_val |
auto[1] |
24148 |
1 |
|
|
T1 |
13 |
|
T3 |
42 |
|
T34 |
20 |
higher_val |
lower_val |
auto[0] |
37557 |
1 |
|
|
T1 |
35 |
|
T2 |
26 |
|
T32 |
4 |
higher_val |
lower_val |
auto[1] |
24152 |
1 |
|
|
T1 |
21 |
|
T3 |
46 |
|
T34 |
21 |
higher_val |
zero_val |
auto[0] |
80 |
1 |
|
|
T15 |
3 |
|
T13 |
1 |
|
T194 |
1 |
higher_val |
zero_val |
auto[1] |
47981 |
1 |
|
|
T1 |
17 |
|
T3 |
111 |
|
T34 |
27 |
lower_val |
higher_val |
auto[0] |
36723 |
1 |
|
|
T1 |
33 |
|
T2 |
32 |
|
T32 |
4 |
lower_val |
higher_val |
auto[1] |
23793 |
1 |
|
|
T1 |
12 |
|
T3 |
44 |
|
T34 |
22 |
lower_val |
lower_val |
auto[0] |
36901 |
1 |
|
|
T1 |
36 |
|
T2 |
46 |
|
T32 |
1 |
lower_val |
lower_val |
auto[1] |
23964 |
1 |
|
|
T1 |
16 |
|
T3 |
47 |
|
T34 |
21 |
lower_val |
zero_val |
auto[0] |
78 |
1 |
|
|
T3 |
1 |
|
T34 |
1 |
|
T37 |
1 |
lower_val |
zero_val |
auto[1] |
47782 |
1 |
|
|
T1 |
28 |
|
T3 |
92 |
|
T34 |
20 |
zero_val |
higher_val |
auto[0] |
532 |
1 |
|
|
T1 |
2 |
|
T7 |
2 |
|
T18 |
1 |
zero_val |
higher_val |
auto[1] |
169 |
1 |
|
|
T91 |
2 |
|
T14 |
2 |
|
T86 |
1 |
zero_val |
lower_val |
auto[0] |
492 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T32 |
1 |
zero_val |
lower_val |
auto[1] |
132 |
1 |
|
|
T1 |
2 |
|
T15 |
1 |
|
T194 |
1 |
zero_val |
zero_val |
auto[0] |
261 |
1 |
|
|
T1 |
2 |
|
T3 |
1 |
|
T34 |
1 |
zero_val |
zero_val |
auto[1] |
228 |
1 |
|
|
T86 |
1 |
|
T87 |
1 |
|
T15 |
1 |