Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msg_len_cg

Group : kmac_env_pkg::kmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
msg_len	15	0	15	100.00	100	1	1	0

Summary for Variable msg_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	10239	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_7501_10000	8637	1			T1	7		T3	19		T34	22
len_5001_7500	13481	1			T1	11		T3	18		T34	66
len_2501_5000	9024	1			T3	18		T34	10		T126	18
len_1025_2500	5258	1			T3	11		T34	9		T126	11
len_769_1024	6237	1			T1	29		T2	25		T3	2
len_513_768	6617	1			T1	38		T2	19		T3	2
len_257_512	21102	1			T1	36		T2	14		T3	2
len_0_256	253885	1			T1	93		T2	20		T3	274
len_keccak_block_sizes[72]	719	1			T3	2		T126	2		T38	1
len_keccak_block_sizes[104]	620	1			T3	2		T36	2		T126	2
len_keccak_block_sizes[136]	513	1			T3	2		T126	2		T91	2
len_keccak_block_sizes[144]	419	1			T85	3		T87	3		T133	2
len_keccak_block_sizes[168]	313	1			T85	3		T87	3		T194	3
len_1	756	1			T3	2		T48	1		T126	2
len_0	1148	1			T1	4		T3	2		T34	5