Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	98321593	1			T1	59376		T2	12519		T3	213691
all_pins[1]	98321593	1			T1	59376		T2	12519		T3	213691
all_pins[2]	98321593	1			T1	59376		T2	12519		T3	213691

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	294185064	1			T1	177738		T2	37426		T3	640536
values[0x1]	779715	1			T1	390		T2	131		T3	537
transitions[0x0=>0x1]	777731	1			T1	390		T2	131		T3	537
transitions[0x1=>0x0]	777752	1			T1	390		T2	131		T3	537

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	97821808	1			T1	59066		T2	12409		T3	213154
all_pins[0]	values[0x1]	499785	1			T1	310		T2	110		T3	537
all_pins[0]	transitions[0x0=>0x1]	499776	1			T1	310		T2	110		T3	537
all_pins[0]	transitions[0x1=>0x0]	5759	1			T1	80		T2	21		T33	2
all_pins[1]	values[0x0]	98315825	1			T1	59296		T2	12498		T3	213691
all_pins[1]	values[0x1]	5768	1			T1	80		T2	21		T33	2
all_pins[1]	transitions[0x0=>0x1]	5493	1			T1	80		T2	21		T33	2
all_pins[1]	transitions[0x1=>0x0]	273887	1			T19	152		T14	525		T15	5127
all_pins[2]	values[0x0]	98047431	1			T1	59376		T2	12519		T3	213691
all_pins[2]	values[0x1]	274162	1			T19	152		T14	526		T15	5136
all_pins[2]	transitions[0x0=>0x1]	272462	1			T19	152		T14	523		T15	5105
all_pins[2]	transitions[0x1=>0x0]	498106	1			T1	310		T2	110		T3	537