Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10403605 |
1 |
|
|
T1 |
28763 |
|
T2 |
14903 |
|
T3 |
2992 |
auto[1] |
10403550 |
1 |
|
|
T1 |
28763 |
|
T2 |
14903 |
|
T3 |
2992 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
20574397 |
1 |
|
|
T1 |
57254 |
|
T2 |
29700 |
|
T3 |
5984 |
triple_byte_access |
77210 |
1 |
|
|
T1 |
90 |
|
T2 |
48 |
|
T7 |
20 |
halfword_access |
78072 |
1 |
|
|
T1 |
102 |
|
T2 |
30 |
|
T7 |
8 |
byte_access |
77476 |
1 |
|
|
T1 |
80 |
|
T2 |
28 |
|
T7 |
22 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10287226 |
1 |
|
|
T1 |
28627 |
|
T2 |
14850 |
|
T3 |
2992 |
auto[0] |
triple_byte_access |
38605 |
1 |
|
|
T1 |
45 |
|
T2 |
24 |
|
T7 |
10 |
auto[0] |
halfword_access |
39036 |
1 |
|
|
T1 |
51 |
|
T2 |
15 |
|
T7 |
4 |
auto[0] |
byte_access |
38738 |
1 |
|
|
T1 |
40 |
|
T2 |
14 |
|
T7 |
11 |
auto[1] |
word_access |
10287171 |
1 |
|
|
T1 |
28627 |
|
T2 |
14850 |
|
T3 |
2992 |
auto[1] |
triple_byte_access |
38605 |
1 |
|
|
T1 |
45 |
|
T2 |
24 |
|
T7 |
10 |
auto[1] |
halfword_access |
39036 |
1 |
|
|
T1 |
51 |
|
T2 |
15 |
|
T7 |
4 |
auto[1] |
byte_access |
38738 |
1 |
|
|
T1 |
40 |
|
T2 |
14 |
|
T7 |
11 |