Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	99138442	1			T1	201707		T3	110012		T36	76490
all_values[1]	99138442	1			T1	201707		T3	110012		T36	76490
all_values[2]	99138442	1			T1	201707		T3	110012		T36	76490

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

556683

1

T1

10

T3

3

T36

2316

auto[1]

296858643

1

T1

605111

T3

330033

T36

227154

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

295888734

1

T1

603408

T3

328941

T36

229266

auto[1]

1526592

1

T1

1713

T3

1095

T36

204

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	169090	1			T1	1		T3	1		T37	5
all_values[0]	auto[0]	auto[1]	2002	1			T1	2		T3	2		T37	2
all_values[0]	auto[1]	auto[0]	98460488	1			T1	201135		T3	109646		T36	76422
all_values[0]	auto[1]	auto[1]	506862	1			T1	569		T3	363		T36	68
all_values[1]	auto[0]	auto[0]	204555	1			T39	5		T7	551		T8	355
all_values[1]	auto[0]	auto[1]	1590	1			T39	2		T7	4		T8	3
all_values[1]	auto[1]	auto[0]	98425023	1			T1	201136		T3	109647		T36	76422
all_values[1]	auto[1]	auto[1]	507274	1			T1	571		T3	365		T36	68
all_values[2]	auto[0]	auto[0]	177802	1			T1	4		T36	2315		T39	2
all_values[2]	auto[0]	auto[1]	1644	1			T1	3		T36	1		T39	1
all_values[2]	auto[1]	auto[0]	98451776	1			T1	201132		T3	109647		T36	74107
all_values[2]	auto[1]	auto[1]	507220	1			T1	568		T3	365		T36	67