Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
349682 |
1 |
|
|
T1 |
2 |
|
T3 |
492 |
|
T36 |
94 |
auto[1] |
341712 |
1 |
|
|
T1 |
746 |
|
T37 |
266 |
|
T7 |
132 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
172623 |
1 |
|
|
T1 |
166 |
|
T3 |
121 |
|
T36 |
20 |
lower_val |
171984 |
1 |
|
|
T1 |
202 |
|
T3 |
148 |
|
T36 |
30 |
zero_val |
1768 |
1 |
|
|
T1 |
3 |
|
T3 |
1 |
|
T36 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
260166 |
1 |
|
|
T1 |
196 |
|
T3 |
260 |
|
T36 |
40 |
lower_val |
260214 |
1 |
|
|
T1 |
200 |
|
T3 |
232 |
|
T36 |
54 |
zero_val |
171014 |
1 |
|
|
T1 |
352 |
|
T37 |
156 |
|
T7 |
54 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
43715 |
1 |
|
|
T3 |
54 |
|
T36 |
6 |
|
T38 |
67 |
higher_val |
higher_val |
auto[1] |
21244 |
1 |
|
|
T1 |
42 |
|
T37 |
11 |
|
T7 |
14 |
higher_val |
lower_val |
auto[0] |
43713 |
1 |
|
|
T3 |
67 |
|
T36 |
14 |
|
T38 |
45 |
higher_val |
lower_val |
auto[1] |
21412 |
1 |
|
|
T1 |
52 |
|
T37 |
12 |
|
T7 |
8 |
higher_val |
zero_val |
auto[0] |
76 |
1 |
|
|
T41 |
1 |
|
T11 |
1 |
|
T199 |
1 |
higher_val |
zero_val |
auto[1] |
42463 |
1 |
|
|
T1 |
72 |
|
T37 |
29 |
|
T7 |
15 |
lower_val |
higher_val |
auto[0] |
43519 |
1 |
|
|
T3 |
87 |
|
T36 |
9 |
|
T38 |
60 |
lower_val |
higher_val |
auto[1] |
21439 |
1 |
|
|
T1 |
46 |
|
T37 |
16 |
|
T7 |
9 |
lower_val |
lower_val |
auto[0] |
43218 |
1 |
|
|
T3 |
61 |
|
T36 |
21 |
|
T38 |
60 |
lower_val |
lower_val |
auto[1] |
21347 |
1 |
|
|
T1 |
57 |
|
T37 |
11 |
|
T7 |
7 |
lower_val |
zero_val |
auto[0] |
83 |
1 |
|
|
T200 |
1 |
|
T201 |
1 |
|
T202 |
1 |
lower_val |
zero_val |
auto[1] |
42378 |
1 |
|
|
T1 |
99 |
|
T37 |
25 |
|
T7 |
8 |
zero_val |
higher_val |
auto[0] |
560 |
1 |
|
|
T36 |
1 |
|
T38 |
1 |
|
T39 |
6 |
zero_val |
higher_val |
auto[1] |
116 |
1 |
|
|
T40 |
1 |
|
T41 |
2 |
|
T203 |
2 |
zero_val |
lower_val |
auto[0] |
545 |
1 |
|
|
T3 |
1 |
|
T39 |
1 |
|
T8 |
1 |
zero_val |
lower_val |
auto[1] |
123 |
1 |
|
|
T1 |
1 |
|
T8 |
1 |
|
T200 |
1 |
zero_val |
zero_val |
auto[0] |
238 |
1 |
|
|
T1 |
1 |
|
T37 |
1 |
|
T41 |
1 |
zero_val |
zero_val |
auto[1] |
186 |
1 |
|
|
T1 |
1 |
|
T8 |
1 |
|
T40 |
1 |