Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msg_len_cg

Group : kmac_env_pkg::kmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
msg_len	15	0	15	100.00	100	1	1	0

Summary for Variable msg_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	10344	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_7501_10000	8999	1			T1	19		T36	8		T37	30
len_5001_7500	14697	1			T1	18		T3	33		T36	26
len_2501_5000	9262	1			T1	18		T3	34		T36	6
len_1025_2500	5392	1			T1	11		T3	20		T36	4
len_769_1024	6105	1			T1	2		T3	4		T38	4
len_513_768	6487	1			T1	2		T3	3		T38	3
len_257_512	21179	1			T1	2		T3	4		T36	1
len_0_256	256477	1			T1	274		T3	148		T36	2
len_keccak_block_sizes[72]	718	1			T1	2		T3	2		T38	2
len_keccak_block_sizes[104]	627	1			T1	2		T39	3		T40	3
len_keccak_block_sizes[136]	521	1			T1	2		T39	3		T7	1
len_keccak_block_sizes[144]	421	1			T39	3		T40	3		T43	2
len_keccak_block_sizes[168]	329	1			T39	3		T40	3		T22	1
len_1	740	1			T1	2		T3	2		T38	2
len_0	1215	1			T1	2		T3	2		T36	1