Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msgfifo_level_cg

Group : kmac_env_pkg::kmac_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

---

Summary for Group kmac_env_pkg::kmac_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hash_mode	3	0	3	100.00	100	1	1	0
kmac_mode	2	0	2	100.00	100	1	1	2
msgfifo_depth	11	0	11	100.00	100	1	1	0
msgfifo_empty	2	0	2	100.00	100	1	1	2
msgfifo_full	2	0	2	100.00	100	1	1	2

Summary for Variable hash_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for hash_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
cshake	16343048	1			T36	65144		T37	165647		T7	4170
shake	57340102	1			T36	17868		T37	55301		T39	493108
sha3	35163860	1			T1	200958		T3	109519		T36	1576

---

Summary for Variable kmac_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_mode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

92502990

1

T1

200958

T3

109519

T36

19444

auto[1]

16344020

1

T36

65144

T37

165647

T7

4175

---

Summary for Variable msgfifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for msgfifo_depth

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
depth[0x00]	91251083	1			T1	198676		T3	107326		T36	65543
depth[0x01]	3720393	1			T1	2282		T3	2193		T36	4193
depth[0x02]	3378661	1			T36	4489		T38	13001		T37	24593
depth[0x03]	3164703	1			T36	4262		T38	12257		T37	23521
depth[0x04]	2850515	1			T36	3388		T38	11756		T37	21325
depth[0x05]	1674111	1			T36	1699		T38	5995		T37	20314
depth[0x06]	572649	1			T36	100		T37	20478		T39	3
depth[0x07]	472760	1			T36	80		T37	17439		T22	2
depth[0x08]	466868	1			T36	107		T37	17597		T22	2
depth[0x09]	446981	1			T36	84		T37	16475		T22	3
depth[0x0a]	848286	1			T36	643		T37	25516		T22	481

---

Summary for Variable msgfifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for msgfifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17595927

1

T1

2282

T3

2193

T36

19045

auto[1]

91251083

1

T1

198676

T3

107326

T36

65543

---

Summary for Variable msgfifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for msgfifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

107998724

1

T1

200958

T3

109519

T36

83945

auto[1]

848286

1

T36

643

T37

25516

T22

481