Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	99138442	1			T1	201707		T3	110012		T36	76490
all_pins[1]	99138442	1			T1	201707		T3	110012		T36	76490
all_pins[2]	99138442	1			T1	201707		T3	110012		T36	76490

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	296596349	1			T1	604552		T3	329673		T36	229376
values[0x1]	818977	1			T1	569		T3	363		T36	94
transitions[0x0=>0x1]	816851	1			T1	569		T3	363		T36	94
transitions[0x1=>0x0]	816872	1			T1	569		T3	363		T36	94

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	98631580	1			T1	201138		T3	109649		T36	76422
all_pins[0]	values[0x1]	506862	1			T1	569		T3	363		T36	68
all_pins[0]	transitions[0x0=>0x1]	506851	1			T1	569		T3	363		T36	68
all_pins[0]	transitions[0x1=>0x0]	5779	1			T36	26		T37	34		T41	17
all_pins[1]	values[0x0]	99132652	1			T1	201707		T3	110012		T36	76464
all_pins[1]	values[0x1]	5790	1			T36	26		T37	34		T41	17
all_pins[1]	transitions[0x0=>0x1]	5514	1			T36	26		T37	34		T41	17
all_pins[1]	transitions[0x1=>0x0]	306049	1			T8	829		T22	585		T23	286
all_pins[2]	values[0x0]	98832117	1			T1	201707		T3	110012		T36	76490
all_pins[2]	values[0x1]	306325	1			T8	829		T22	585		T23	286
all_pins[2]	transitions[0x0=>0x1]	304486	1			T8	829		T22	585		T23	286
all_pins[2]	transitions[0x1=>0x0]	505044	1			T1	569		T3	363		T36	68