Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	628	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5461	1			T36	4		T37	17		T7	3
len_601_800	12478	1			T36	23		T37	42		T7	15
len_401_600	8495	1			T36	8		T37	36		T7	13
len_201_400	16537	1			T36	5		T37	14		T39	251
len_65_200	73406	1			T36	4		T37	11		T39	680
len_min_for_xof_require_squeeze	1001	1			T37	1		T39	10		T40	9
len_keccak_block_sizes[72]	752	1			T39	5		T40	9		T83	5
len_keccak_block_sizes[104]	757	1			T39	5		T40	9		T23	1
len_keccak_block_sizes[136]	736	1			T39	5		T40	9		T83	5
len_keccak_block_sizes[144]	281	1			T39	5		T83	5		T84	5
len_keccak_block_sizes[168]	285	1			T39	5		T83	5		T84	5
len_datapath_width	13886	1			T3	246		T38	246		T37	1
len_2_63	213375	1			T1	374		T36	2		T37	11
len_1	60	1			T8	1		T204	1		T205	2