Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	99721248	1			T2	222065		T3	382		T39	206031
all_values[1]	99721248	1			T2	222065		T3	382		T39	206031
all_values[2]	99721248	1			T2	222065		T3	382		T39	206031

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

438008

1

T2

10

T3

50

T39

7

auto[1]

298725736

1

T2

666185

T3

1096

T39

618086

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

297636141

1

T2

664413

T3

1005

T39

616386

auto[1]

1527603

1

T2

1782

T3

141

T39

1707

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	143906	1			T2	3		T3	23		T38	62
all_values[0]	auto[0]	auto[1]	1926	1			T2	4		T3	2		T38	6
all_values[0]	auto[1]	auto[0]	99068141	1			T2	221468		T3	312		T39	205462
all_values[0]	auto[1]	auto[1]	507275	1			T2	590		T3	45		T39	569
all_values[1]	auto[0]	auto[0]	122794	1			T2	1		T39	5		T38	4
all_values[1]	auto[0]	auto[1]	1354	1			T2	2		T39	2		T38	2
all_values[1]	auto[1]	auto[0]	99089253	1			T2	221470		T3	335		T39	205457
all_values[1]	auto[1]	auto[1]	507847	1			T2	592		T3	47		T39	567
all_values[2]	auto[0]	auto[0]	166527	1			T3	23		T38	62		T40	2
all_values[2]	auto[0]	auto[1]	1501	1			T3	2		T38	6		T40	1
all_values[2]	auto[1]	auto[0]	99045520	1			T2	221471		T3	312		T39	205462
all_values[2]	auto[1]	auto[1]	507700	1			T2	594		T3	45		T39	569